The invention relates to fabrication of integrated circuit memory devices. More specifically, the invention relates to forming transistors in flash technology and devices formed thereby.
The semiconductor community faces increasingly difficult challenges as it moves into production of continually smaller semiconductor devices. Memory cell designs for typical semiconductor memory devices must be made more durable, smaller (i.e., scalable), cost effective to manufacture, faster in reading and writing and capable of operating at low or high voltages. Given the considerable commercial importance placed on small memory cell size and reliability of such devices, new fabrication processes are continually needed.
In general, memory devices such as a flash electrically erasable programmable read only memory (EEPROM) are known. EEPROMs are a class of nonvolatile memory devices that are programmed by hot electron injection and erased by Fowler-Nordheim tunneling. Each memory cell is formed on a semiconductor substrate (i.e., a silicon die or chip), having a heavily doped drain region and a source region embedded therein. A channel region separates the drain region and the source region.
The memory cell further includes a multi-layer structure, commonly referred to as a xe2x80x9cstacked gatexe2x80x9d structure or word line. The stacked gate structure typically includes: a thin gate dielectric or tunnel oxidation layer formed on the surface of substrate overlying the channel region; a first polysilicon (poly 1) floating gate overlying the tunnel oxidation; an interpoly dielectric overlying the floating gate; and a second polysilicon (poly 2) control gate overlying the interpoly dielectric layer. Additional layers may be formed by salicidation on the control gate polysilicon. A plurality of flash memory cells may be formed on a single substrate.
Conventional flash memory devices also include peripheral portions, which typically include input/output circuitry for selectively addressing individual memory cells. Clearly, each memory device requires multiple transistors. Such transistors need not only be relatively small but the fabrication process cost effective, preferably simple and resulting in reliable devices. In particular, conventional flash technology forms high voltage (HV) peripheral transistors using only the second polysilicon gate (i.e., the control gate polysilicon-poly 2) or an unsalicided poly 1 gate. This conventional approach limits the number of devices available for circuit design and complicates the processing steps necessary for reliable HV device performance. Although high voltage poly 1 gate transistors have been fabricated in flash technology, the currently available methods form only unsalicided devices due to processing limitations. Specifically, only unsalicided poly 1 gate transistors have been formed to date for flash technology devices due to the unacceptable thinning of poly 1 from repeated oxidation and etching of subsequent oxides formed, as well as the low etch selectivity between oxide and polysilicon.
Presently disclosed are high voltage (HV) (i.e., capable of operating at or greater than about 5.0 V), memory devices including, e.g., single polysilicon (poly) gate NMOS and PMOS transistors in double polysilicon stacked gate flash technology and methods for fabricating the same. Specifically, disclosed are double poly stacked gate flash memory devices having high voltage poly 1 transistors and poly 2 transistors (NMOS and PMOS) in double polysilicon stacked gate flash technology. Certain embodiments of the methods allow for formation of different types of transistors (e.g., HV P1 NMOS, HV P1 PMOS, HV P2 NMOS, HV P2 PMOS, LV P1 NMOS, LV P1 PMOS, LV P2 NMOS, LV P2 PMOS) providing versatility in flash device design. Certain embodiments of the single poly transistors may be salicided without adding to the complexity of the double poly stacked gate fabrication process. Certain embodiments of the methods overcome the current limitations of fabricating high voltage devices using only poly 2 gates or fabricating high voltage poly 1 transistors that are unsalicided, in double poly stacked gate flash technology.
For example, in an embodiment of the fabrication process for forming a flash memory cell, the method comprises providing a substrate; forming a double polysilicon stacked gate device on the substrate, including a first polysilicon layer and a second polysilicon layer; formning a high voltage NMOS or PMOS first transistor on the substrate, the high voltage NMOS or PMOS first transistor including a gate formed by the first polysilicon layer; forming a high voltage or low voltage NMOS or PMOS second transistor on the substrate, the NMOS or PMOS second transistor including a gate formed by the second polysilicon layer; and saliciding the double polysilicon stacked gate device, the high voltage NMOS or PMOS first transistor, and the high voltage or low voltage second NMOS or PMOS transistor.
Certain embodiments of the disclosed double poly stacked gate flash technology memory devices comprise single poly 1 gate NMOS and PMOS transistors. Specifically, certain embodiments of the devices comprise high voltage peripheral poly 1 transistors in double stacked gate devices and/or salicided poly 1 transistors in double stacked gate devices. xe2x80x9cPeripheralxe2x80x9d is used herein as relative to xe2x80x9cCORE.xe2x80x9d A CORE device refers to a stacked-gate transistor, while peripheral devices refer to regular single poly transistors (e.g., P1 or P2, LV or HV, etc.). As is known to those persons of ordinary skill in the art, salicided poly 1 devices provide lower S/D and parasitic resistence, higher drive current and thus, provide superior performing transistors.